TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O – MARCH 1999 – REVISED JANUARY 2005
www.ti.com
5.3
Electrical Characteristics
The electrical charactheristics are measured over recommended operating case temperature range (unless otherwise noted).
All values are typical unless otherwise specified.
PARAMETER
V
OH
V
OL
High-level output voltage
(1)
Low-level output voltage
(1)
X2/CLKIN
TRST, HPI16
I
I
Input current (V
I
=
DV
SS
to DV
DD
)
HPIENA
TMS, TCK, TDI, HPI
(2)
A[17:0], D[15:0],
HD[7:0]
All other input-only pins
I
DDC
I
DDP
I
DD
C
i
C
o
(1)
(2)
(3)
(4)
(5)
(6)
Supply current, core CPU
Supply current, pins
IDLE2
Supply current,
standby
Input capacitance
Output capacitance
IDLE3 Divide-by-two
mode, CLKIN stopped
CV
DD
= 1.6 V, f
x
= 160 ,
(4)
T
C
= 25°C
DV
DD
= 3.0 V, f
x
= 160 MHz,
(4)
T
C
= 25°C
PLL
×
1 mode, 20 MHz input
T
C
= 25°C
T
C
= 100°C
With internal pulldown
With internal pulldown, RS = 0
With internal pullups
Bus holders enabled, DV
DD
= MAX
(3)
TEST CONDITIONS
DV
DD
= 2.7 V to 3 V, I
OH
= -2 mA
DV
DD
= 3 V to 3.6 V, I
OH
= MAX
I
OL
= MAX
– 40
– 10
– 10
– 400
– 275
–5
60
(5)
40
(6)
2
1
30
5
5
pF
pF
mA
MIN
2.2
2.4
0.4
40
800
400
10
275
5
mA
mA
µA
TYP
MAX
UNIT
V
V
µA
All input and output voltage levels except RS, INT0-INT3, NMI, X2/CLKIN, CLKMD1-CLKMD3, BCLKRn, BCLKXn, HCS, HAS, HDS1,
HDS2, BIO, TCK, TRST, Dn, An, HDn are LVTTL-compatible.
HPI input signals except for HPIENA and HPI16, when HPIENA = 0.
V
IL(MIN)
≤V
I
≤V
IL(MAX)
or V
IH(MIN)
≤
V
I
≤
V
IH(MAX)
Clock mode: PLL
×
1 with external source
This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program
being executed.
This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is
performed, refer to the
Calculation of TMS320LC54x Power Dissipation
application report (literature number SPRA164).
5.3.1
Test Loading
Tester Pin Electronics
Data Sheet Timing Reference Point
42
W
3.5 nH
Transmission Line
Z0 = 50
W
(see note)
Output
Under
Test
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The
transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data
sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 5-1. Tester Pin Electronics
54
Electrical Specifications
TI [ TEXAS INSTRUMENTS ]
