ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢈꢈ ꢉ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢊ
ꢋ ꢌ ꢍꢎꢏ ꢐꢑ ꢒꢌ ꢓ ꢀ ꢏ ꢌ ꢔꢌ ꢀꢕꢖ ꢂ ꢌ ꢔꢓ ꢕꢖ ꢑ ꢗꢒ ꢆꢎꢂ ꢂꢒ ꢗꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
signal groups description
CLKIN
CLKOUT2
RESET
NMI
CLKOUT1
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
Reset and
Interrupts
CLKMODE0
Clock/PLL
PLLV
PLLG
PLLF
TMS
TDO
TDI
RSV5
RSV4
RSV3
RSV2
RSV1
RSV0
TCK
IEEE Standard
1149.1
(JTAG)
Emulation
TRST
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
Reserved
Control/Status
HPI
16
(Host-Port Interface)
HD[15:0]
Data
HAS
HCNTL0
HCNTL1
HR/W
HCS
HDS1
HDS2
HRDY
HINT
Register Select
Control
Half-Word
Select
HHWIL
Figure 2. CPU (DSP Core) and Peripheral Signals
20
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