ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢈꢈꢊ
ꢋ ꢌꢍ ꢎꢏꢐꢑꢒ ꢌ ꢓꢀ ꢏꢌ ꢔꢌ ꢀꢕꢖ ꢂꢌ ꢔ ꢓꢕꢖ ꢑꢗ ꢒ ꢆꢎ ꢂ ꢂꢒ ꢗ ꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
PWRD bits in CPU CSR register description
Table 14 identifies the PWRD field (bits 15−10) in the CPU CSR register. These bits control the device
power-down modes. For more detailed information on the PWRD bit field of the CPU CSR register, see the
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Table 14. PWRD field bits in the CPU CSR Register
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The PWRD field (bits 15−10 in the CPU CSR)
controls the device power-down modes.
−
CSR
Control status register
Accessible by writing a value to the CSR register.
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