ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢈꢈ ꢉ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢊ
ꢋ ꢌ ꢍꢎꢏ ꢐꢑ ꢒꢌ ꢓ ꢀ ꢏ ꢌ ꢔꢌ ꢀꢕꢖ ꢂ ꢌ ꢔꢓ ꢕꢖ ꢑ ꢗꢒ ꢆꢎꢂ ꢂꢒ ꢗꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
Terminal Functions (Continued)
SIGNAL
IPD/
†
TYPE
DESCRIPTION
‡
IPU
NAME
NO.
EMIF − BUS ARBITRATION
Hold-request-acknowledge to the host
Hold request from the host
HOLDA
J18
J17
J19
O
I
IPU
IPU
IPU
HOLD
BUSREQ
O
Bus request output
EMIF − ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL
ECLKIN
Y11
Y10
I
IPD
IPD
EMIF input clock
ECLKOUT
O
EMIF output clock (based on ECLKIN)
ARE/SDCAS/
SSADS
V11
O/Z
O/Z
IPU
IPU
Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe
Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable
Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable
AOE/SDRAS/
SSOE
W10
AWE/SDWE/
SSWE
V12
Y5
O/Z
I
IPU
IPU
ARDY
Asynchronous memory ready input
EMIF − ADDRESS
EA21
EA20
EA19
EA18
EA17
EA16
EA15
EA14
EA13
EA12
EA11
EA10
EA9
U18
Y18
W17
Y16
V16
Y15
W15
Y14
W14
V14
W13
V10
Y9
O/Z
IPU
EMIF external address
EA8
V9
EA7
Y8
EA6
W8
V8
EA5
EA4
W7
V7
EA3
EA2
Y6
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
24
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