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TMS320VC5407 参数 Datasheet PDF下载

TMS320VC5407图片预览
型号: TMS320VC5407
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [Fixed-Point Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 110 页 / 1351 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Functional Overview  
3.18 DMA Subbank Addressed Registers  
The direct memory access (DMA) controller has several control registers associated with it. The main control  
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using  
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single  
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular  
register within the subbank, while the DMA subbank data (DMSD) register or the DMA subbank data register  
with autoincrement (DMSDI) is used to access (read or write) the selected register.  
When the DMSDI register is used to access the subbank, the subbank address is automatically  
postincremented so that a subsequent access affects the next register within the subbank. This autoincrement  
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature  
is not required, the DMSDN register should be used to access the subbank. Table 326 shows the DMA  
controller subbank addressed registers and their corresponding subaddresses.  
Table 326. DMA Subbank Addressed Registers  
SUB-  
NAME  
ADDRESS  
DESCRIPTION  
ADDRESS  
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
0Dh  
0Eh  
0Fh  
10h  
11h  
DMSRC0  
DMDST0  
DMCTR0  
DMSFC0  
DMMCR0  
DMSRC1  
DMDST1  
DMCTR1  
DMSFC1  
DMMCR1  
DMSRC2  
DMDST2  
DMCTR2  
DMSFC2  
DMMCR2  
DMSRC3  
DMDST3  
DMCTR3  
DMSFC3  
DMMCR3  
DMSRC4  
DMDST4  
DMCTR4  
DMSFC4  
DMMCR4  
DMSRC5  
DMDST5  
DMCTR5  
DMSFC5  
DMMCR5  
DMSRCP  
DMDSTP  
DMIDX0  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
56h/57h  
DMA channel 0 source address register  
DMA channel 0 destination address register  
DMA channel 0 element count register  
DMA channel 0 sync select and frame count register  
DMA channel 0 transfer mode control register  
DMA channel 1 source address register  
DMA channel 1 destination address register  
DMA channel 1 element count register  
DMA channel 1 sync select and frame count register  
DMA channel 1 transfer mode control register  
DMA channel 2 source address register  
DMA channel 2 destination address register  
DMA channel 2 element count register  
DMA channel 2 sync select and frame count register  
DMA channel 2 transfer mode control register  
DMA channel 3 source address register  
DMA channel 3 destination address register  
DMA channel 3 element count register  
12h  
13h  
14h  
15h  
16h  
17h  
18h  
19h  
1Ah  
1Bh  
1Ch  
1Dh  
1Eh  
1Fh  
20h  
DMA channel 3 sync select and frame count register  
DMA channel 3 transfer mode control register  
DMA channel 4 source address register  
DMA channel 4 destination address register  
DMA channel 4 element count register  
DMA channel 4 sync select and frame count register  
DMA channel 4 transfer mode control register  
DMA channel 5 source address register  
DMA channel 5 destination address register  
DMA channel 5 element count register  
DMA channel 5 sync select and frame count register  
DMA channel 5 transfer mode control register  
DMA source program page address (common channel)  
DMA destination program page address (common channel)  
DMA element index address register 0  
64  
SPRS007D  
November 2001 Revised April 2004  
 
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