Functional Overview
Table 3−24. Peripheral Memory-Mapped Registers for Each DSP Subsystem
ADDRESS
NAME
DESCRIPTION
DEC
HEX
DRR20
DRR10
DXR20
DXR10
TIM
32
20
McBSP 0 Data Receive Register 2
McBSP 0 Data Receive Register 1
McBSP 0 Data Transmit Register 2
McBSP 0 Data Transmit Register 1
Timer 0 Register
33
34
21
22
35
36
23
24
PRD
37
25
Timer 0 Period Register
TCR
38
26
Timer 0 Control Register
—
39
27
Reserved
SWWSR
BSCR
—
40
41
28
29
Software Wait-State Register
Bank-Switching Control Register
Reserved
42
2A
SWCR
HPIC
—
43
2B
Software Wait-State Control Register
HPI Control Register (HMODE = 0 only)
Reserved
44
45−47
48
2C
2D−2F
30
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
—
SPSA0
SPSD0
—
McBSP 2 Data Receive Register 2
McBSP 2 Data Receive Register 1
McBSP 2 Data Transmit Register 2
McBSP 2 Data Transmit Register 1
49
50
31
32
51
52
33
34
†
McBSP 2 Subbank Address Register
†
53
54−55
56
35
36−37
38
McBSP 2 Subbank Data Register
Reserved
McBSP 0 Subbank Address Register
†
†
57
58−59
60
39
3A−3B
3C
McBSP 0 Subbank Data Register
Reserved
GPIOCR
GPIOSR
CSIDR
—
General-Purpose I/O Control Register
General-Purpose I/O Status Register
Device ID Register
61
3D
62
63
3E
3F
Reserved
DRR21
DRR11
DXR21
DXR11
USAR
USDR
—
SPSA1
SPSD1
—
64
40
McBSP 1 Data Receive Register 2
McBSP 1 Data Receive Register 1
McBSP 1 Data Transmit Register 2
McBSP 1 Data Transmit Register 1
UART Subbank Address Register
UART Subbank Data Register
Reserved
65
66
41
42
67
68
43
44
69
70−71
72
45
46−47
48
†
McBSP 1 Subbank Address Register
†
73
74−75
76
49
4A−4B
4C
McBSP 1 Subbank Data Register
Reserved
TIM1
Timer 1 Register
PRD1
TCR1
—
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
—
77
4D
Timer 1 Period Register
Timer 1 Control Register
Reserved
78
79−83
84
4E
4F−53
54
DMA Priority and Enable Control Register
‡
85
86
55
56
DMA Subbank Address Register
DMA Subbank Data Register with Autoincrement
‡
‡
87
88
57
58
DMA Subbank Data Register
Clock Mode Register (CLKMD)
Reserved
89−95
59−5F
†
See Table 3−25 for a detailed description of the McBSP control registers and their subaddresses.
See Table 3−26 for a detailed description of the DMA subbank addressed registers.
‡
62
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
