Functional Overview
3.19.1 IFR and IMR Registers
The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in Figure 3−26.
15
14
13
12
11
10
9
8
†
Reserved
UART
DMAC5
DMAC4
BXINT1
BRINT1
HINT
INT3
7
6
5
4
3
2
1
0
BXINT2
BRINT2
BXINT0
BRINT0
TINT0
INT2
INT1
INT0
†
Bit 8 reflects the status of either INT3 or TINT1: these two interrupts are ORed together. To distinguish one from the other, one of these two interrupt
sources must be inhibited.
Figure 3−26. IFR and IMR
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November 2001 − Revised April 2004
SPRS007D