Functional Overview
3.16 Memory-Mapped Registers
The 5407/5404 has 27 memory-mapped CPU registers, which are mapped in data memory space address
0h to 1Fh. Each 5407/5404 device also has a set of memory-mapped registers associated with peripherals.
Table 3−23 gives a list of CPU memory-mapped registers (MMRs) available on 5407/5404. Table 3−24 shows
additional peripheral MMRs associated with the 5407/5404.
Table 3−23. CPU Memory-Mapped Registers
ADDRESS
NAME
DESCRIPTION
DEC
0
HEX
0
IMR
IFR
—
Interrupt mask register
Interrupt flag register
Reserved for testing
Status register 0
1
1
2−5
6
2−5
6
ST0
ST1
AL
7
7
Status register 1
8
8
Accumulator A low word (15−0)
AH
9
9
Accumulator A high word (31−16)
Accumulator A guard bits (39−32)
Accumulator B low word (15−0)
Accumulator B high word (31−16)
Accumulator B guard bits (39−32)
Temporary register
AG
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
BL
B
BH
C
BG
D
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
E
F
Transition register
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Auxiliary register 0
Auxiliary register 1
Auxiliary register 2
Auxiliary register 3
Auxiliary register 4
Auxiliary register 5
Auxiliary register 6
Auxiliary register 7
Stack pointer register
BK
Circular buffer size register
Block repeat counter
BRC
RSA
REA
PMST
XPC
—
Block repeat start address
Block repeat end address
Processor mode status (PMST) register
Extended program page register
Reserved
61
November 2001 − Revised April 2004
SPRS007D
TI [ TEXAS INSTRUMENTS ]
