Peripherals
•
•
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as
zeros. Writing to the upper byte has no effect.
Enhanced features:
•
•
Auto baud-detect hardware logic
16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 4−8 and Table 4−9.
†
Table 4−8. SCI-A Registers
NAME
ADDRESS
0x00 7050
0x00 7051
0x00 7052
0x00 7053
0x00 7054
0x00 7055
0x00 7056
0x00 7057
0x00 7059
0x00 705A
0x00 705B
0x00 705C
0x00 705F
SIZE (x16)
DESCRIPTION
SCI-A Communications Control Register
SCI-A Control Register 1
SCICCRA
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA
SCIFFRXA
SCIFFCTA
SCIPRIA
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
†
Shaded registers are new registers for the FIFO mode.
†‡
Table 4−9. SCI-B Registers
NAME
ADDRESS
0x00 7750
0x00 7751
0x00 7752
0x00 7753
0x00 7754
0x00 7755
0x00 7756
0x00 7757
0x00 7759
0x00 775A
0x00 775B
0x00 775C
0x00 775F
SIZE (x16)
DESCRIPTION
SCI-B Communications Control Register
SCI-B Control Register 1
SCICCRB
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1B
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB
SCIFFRXB
SCIFFCTB
SCIPRIB
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
†
‡
Shaded registers are new registers for the FIFO mode.
Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
78
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
