Peripherals
Figure 4−11 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPISTS.7
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
SPIINT/SPIRXINT
RX FIFO Interrupt
−−−−−
RX Interrupt
Logic
RX FIFO _15
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
TX Interrupt
Logic
TX FIFO Interrupt
−−−−−
TX FIFO _1
SPITXINT
TX FIFO _0
16
SPI INT
ENA
SPI INT FLAG
SPITXBUF
Buffer Register
SPISTS.6
SPICTL.0
16
16
M
S
M
SPIDAT
Data Register
S
SW1
SW2
SPISIMO
SPISOMI
M
S
M
SPIDAT.15 − 0
S
Talk
SPICTL.1
†
SPISTE
State Control
Master/Slave
SPICTL.2
SPI Char
SPICCR.3 − 0
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
LSPCLK
SPICCR.6
SPICTL.3
SPICLK
SPIBRR.6 − 0
M
6
5
4
3
2
1
0
†
SPISTE is driven low by the master for a slave device.
Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode)
82
SPRS174L
April 2001 − Revised December 2004