Peripherals
Table 4−7 provides a summary of the McBSP registers.
Table 4−7. McBSP Register Summary
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
DESCRIPTION
†
DATA REGISTERS, RECEIVE, TRANSMIT
−
−
−
−
−
−
−
−
−
0x0000
0x0000
0x0000
McBSP Receive Buffer Register
McBSP Receive Shift Register
McBSP Transmit Shift Register
McBSP Data Receive Register 2
DRR2
DRR1
DXR2
DXR1
00
01
02
03
R
R
0x0000
0x0000
0x0000
0x0000
−
Read First if the word size is greater than 16 bits,
else ignore DRR2
McBSP Data Receive Register 1
−
Read Second if the word size is greater than 16 bits,
else read DRR1 only
McBSP Data Transmit Register 2
−
W
W
Write First if the word size is greater than 16 bits,
else ignore DXR2
McBSP Data Transmit Register 1
−
Write Second if the word size is greater than 16 bits,
else write to DXR1 only
McBSP CONTROL REGISTERS
SPCR2
SPCR1
RCR2
04
05
06
07
08
09
0A
0B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Serial Port Control Register 2
McBSP Serial Port Control Register 1
McBSP Receive Control Register 2
McBSP Receive Control Register 1
McBSP Transmit Control Register 2
McBSP Transmit Control Register 1
McBSP Sample Rate Generator Register 2
McBSP Sample Rate Generator Register 1
RCR1
XCR2
XCR1
SRGR2
SRGR1
MULTICHANNEL CONTROL REGISTERS
MCR2
MCR1
0C
0D
0E
0F
10
11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Multichannel Register 2
McBSP Multichannel Register 1
RCERA
RCERB
XCERA
XCERB
PCR
McBSP Receive Channel Enable Register Partition A
McBSP Receive Channel Enable Register Partition B
McBSP Transmit Channel Enable Register Partition A
McBSP Transmit Channel Enable Register Partition B
McBSP Pin Control Register
12
13
14
15
16
RCERC
RCERD
XCERC
XCERD
McBSP Receive Channel Enable Register Partition C
McBSP Receive Channel Enable Register Partition D
McBSP Transmit Channel Enable Register Partition C
McBSP Transmit Channel Enable Register Partition D
†
‡
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
75
April 2001 − Revised December 2004
SPRS174L
TI [ TEXAS INSTRUMENTS ]
