Peripherals
Table 4−7. McBSP Register Summary (Continued)
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
DESCRIPTION
MULTICHANNEL CONTROL REGISTERS (CONTINUED)
RCERE
RCERF
XCERE
XCERF
RCERG
RCERH
XCERG
XCERH
17
18
19
1A
1B
1C
1D
1E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Receive Channel Enable Register Partition E
McBSP Receive Channel Enable Register Partition F
McBSP Transmit Channel Enable Register Partition E
McBSP Transmit Channel Enable Register Partition F
McBSP Receive Channel Enable Register Partition G
McBSP Receive Channel Enable Register Partition H
McBSP Transmit Channel Enable Register Partition G
McBSP Transmit Channel Enable Register Partition H
FIFO MODE REGISTERS (applicable only in FIFO mode)
‡
FIFO Data Registers
McBSP Data Receive Register 2 − Top of receive FIFO
Read First FIFO pointers will not advance
DRR2
DRR1
DXR2
DXR1
00
01
02
03
R
R
0x0000
−
McBSP Data Receive Register 1 − Top of receive FIFO
Read Second for FIFO pointers to advance
0x0000
0x0000
0x0000
−
McBSP Data Transmit Register 2 − Top of transmit FIFO
Write First FIFO pointers will not advance
W
W
−
McBSP Data Transmit Register 1 − Top of transmit FIFO
−
Write Second for FIFO pointers to advance
FIFO Control Registers
0xA000
MFFTX
MFFRX
MFFCT
MFFINT
MFFST
20
21
22
23
24
R/W
R/W
R/W
R/W
R/W
McBSP Transmit FIFO Register
McBSP Receive FIFO Register
McBSP FIFO Control Register
McBSP FIFO Interrupt Register
McBSP FIFO Status Register
0x201F
0x0000
0x0000
0x0000
†
‡
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
76
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
