Peripherals
Figure 4−9 shows the block diagram of the McBSP module with FIFO, interfaced to the F281x and C281x
version of Peripheral Frame 2.
Peripheral Write Bus
TX FIFO
Interrupt
TX FIFO _15
—
TX FIFO _15
MXINT
—
TX Interrupt Logic
To CPU
TX FIFO _1
TX FIFO _0
TX FIFO _1
TX FIFO _0
McBSP Transmit
Interrupt Select Logic
TX FIFO Registers
16
16
DXR2 Transmit Buffer DXR1 Transmit Buffer
LSPCLK
FSX
McBSP Registers
and Control Logic
16
16
CLKX
Compand Logic
XSR2
XSR1
DX
DR
RSR1
16
RSR2
16
CLKR
Expand Logic
FSR
RBR2 Register
16
RBR1 Register
16
McBSP
DRR2 Receive Buffer
16
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
RX FIFO _15
—
RX FIFO _15
—
RX FIFO
Interrupt
RX FIFO _1
RX FIFO _0
RX FIFO _1
RX FIFO _0
RX Interrupt Logic
MRINT
To CPU
RX FIFO Registers
Peripheral Read Bus
Figure 4−9. McBSP Module With FIFO
74
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
