Peripherals
4.5
Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
•
•
•
•
•
•
•
•
•
•
•
Compatible to McBSP in TMS320C54x /TMS320C55x DSP devices, except the DMA features
Full-duplex communication
Double-buffered data registers which allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
HIghly programmable internal clock and frame generation
Support A-bis mode
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
•
•
•
Works with SPI-compatible devices
Two 16 x 16-level FIFO for Transmit channel
Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
•
•
T1/E1 framers
MVIP switching-compatible and ST-BUS-compliant devices including:
−
−
−
−
−
−
MVIP framers
H.100 framers
SCSA framers
IOM-2 compliant devices
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
IIS-compliant devices
CLKSRG
(1 ) CLKGDIV)
•
McBSP clock rate = CLKG =
, where CLKSRG source could be LSPCLK, CLKX, or
†
CLKR.
TMS320C54x and TMS320C55x are trademarks of Texas Instruments.
†
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less
than the I/O buffer speed limit—20-MHz maximum.
73
April 2001 − Revised December 2004
SPRS174L
TI [ TEXAS INSTRUMENTS ]
