Peripherals
The CAN registers listed in Table 4−6 are used by the CPU to configure and control the CAN controller and
the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
†
Table 4−6. CAN Registers Map
SIZE
(x32)
REGISTER NAME
ADDRESS
DESCRIPTION
CANME
CANMD
0x00 6000
0x00 6002
0x00 6004
0x00 6006
0x00 6008
0x00 600A
0x00 600C
0x00 600E
0x00 6010
0x00 6012
0x00 6014
0x00 6016
0x00 6018
0x00 601A
0x00 601C
0x00 601E
0x00 6020
0x00 6022
0x00 6024
0x00 6026
0x00 6028
0x00 602A
0x00 602C
0x00 602E
0x00 6030
0x00 6032
1
Mailbox enable
1
Mailbox direction
Transmit request set
CANTRS
CANTRR
CANTA
1
1
Transmit request reset
Transmission acknowledge
Abort acknowledge
1
CANAA
1
CANRMP
CANRML
CANRFP
CANGAM
CANMC
1
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
1
1
1
1
CANBTC
CANES
1
Bit-timing configuration
Error and status
1
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
1
Transmit error counter
Receive error counter
1
1
Global interrupt flag 0
1
Global interrupt mask
1
Global interrupt flag 1
1
Mailbox interrupt mask
Mailbox interrupt level
1
1
Overwrite protection control
TX I/O control
1
1
RX I/O control
1
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
1
1
†
These registers are mapped to Peripheral Frame 1.
72
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
