Peripherals
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4−4.
†
Table 4−4. ADC Registers
SIZE
(x16)
NAME
ADDRESS
DESCRIPTION
ADCTRL1
ADCTRL2
0x00 7100
0x00 7101
0x00 7102
0x00 7103
0x00 7104
0x00 7105
0x00 7106
0x00 7107
0x00 7108
0x00 7109
0x00 710A
0x00 710B
0x00 710C
0x00 710D
0x00 710E
0x00 710F
0x00 7110
0x00 7111
0x00 7112
0x00 7113
0x00 7114
0x00 7115
0x00 7116
0x00 7117
0x00 7118
0x00 7119
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADC Control Register 1
ADC Control Register 2
ADCMAXCONV
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
ADCASEQSR
ADCRESULT0
ADCRESULT1
ADCRESULT2
ADCRESULT3
ADCRESULT4
ADCRESULT5
ADCRESULT6
ADCRESULT7
ADCRESULT8
ADCRESULT9
ADCRESULT10
ADCRESULT11
ADCRESULT12
ADCRESULT13
ADCRESULT14
ADCRESULT15
ADCTRL3
ADC Maximum Conversion Channels Register
ADC Channel Select Sequencing Control Register 1
ADC Channel Select Sequencing Control Register 2
ADC Channel Select Sequencing Control Register 3
ADC Channel Select Sequencing Control Register 4
ADC Auto-Sequence Status Register
ADC Conversion Result Buffer Register 0
ADC Conversion Result Buffer Register 1
ADC Conversion Result Buffer Register 2
ADC Conversion Result Buffer Register 3
ADC Conversion Result Buffer Register 4
ADC Conversion Result Buffer Register 5
ADC Conversion Result Buffer Register 6
ADC Conversion Result Buffer Register 7
ADC Conversion Result Buffer Register 8
ADC Conversion Result Buffer Register 9
ADC Conversion Result Buffer Register 10
ADC Conversion Result Buffer Register 11
ADC Conversion Result Buffer Register 12
ADC Conversion Result Buffer Register 13
ADC Conversion Result Buffer Register 14
ADC Conversion Result Buffer Register 15
ADC Control Register 3
ADCST
ADC Status Register
0x00 711C
0x00 711F
reserved
4
†
The above registers are Peripheral Frame 2 Registers.
68
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
