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TMS320F2812PGFQ 参数 Datasheet PDF下载

TMS320F2812PGFQ图片预览
型号: TMS320F2812PGFQ
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号处理器 [Digital Signal Processors]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置PC可编程只读存储器时钟
文件页数/大小: 162 页 / 1979 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Peripherals  
Table 4−3. EVA Registers  
SIZE  
(x16)  
NAME  
ADDRESS  
DESCRIPTION  
GPTCONA  
T1CNT  
T1CMPR  
T1PR  
0x00 7400  
0x00 7401  
0x00 7402  
0x00 7403  
0x00 7404  
0x00 7405  
0x00 7406  
0x00 7407  
0x00 7408  
0x00 7409  
0x00 7411  
0x00 7413  
0x00 7415  
0x00 7417  
0x00 7418  
0x00 7419  
0x00 7420  
0x00 7422  
0x00 7423  
0x00 7424  
0x00 7425  
0x00 7427  
0x00 7428  
0x00 7429  
0x00 742C  
0x00 742D  
0x00 742E  
0x00 742F  
0x00 7430  
0x00 7431  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GP Timer Control Register A  
GP Timer 1 Counter Register  
GP Timer 1 Compare Register  
GP Timer 1 Period Register  
GP Timer 1 Control Register  
GP Timer 2 Counter Register  
GP Timer 2 Compare Register  
GP Timer 2 Period Register  
GP Timer 2 Control Register  
GP Extension Control Register A  
Compare Control Register A  
Compare Action Control Register A  
Dead-Band Timer Control Register A  
Compare Register 1  
T1CON  
T2CNT  
T2CMPR  
T2PR  
T2CON  
EXTCONA  
COMCONA  
ACTRA  
DBTCONA  
CMPR1  
CMPR2  
Compare Register 2  
CMPR3  
Compare Register 3  
CAPCONA  
CAPFIFOA  
CAP1FIFO  
CAP2FIFO  
CAP3FIFO  
CAP1FBOT  
CAP2FBOT  
CAP3FBOT  
EVAIMRA  
EVAIMRB  
EVAIMRC  
EVAIFRA  
EVAIFRB  
EVAIFRC  
Capture Control Register A  
Capture FIFO Status Register A  
Two-Level Deep Capture FIFO Stack 1  
Two-Level Deep Capture FIFO Stack 2  
Two-Level Deep Capture FIFO Stack 3  
Bottom Register Of Capture FIFO Stack 1  
Bottom Register Of Capture FIFO Stack 2  
Bottom Register Of Capture FIFO Stack 3  
Interrupt Mask Register A  
Interrupt Mask Register B  
Interrupt Mask Register C  
Interrupt Flag Register A  
Interrupt Flag Register B  
Interrupt Flag Register C  
The EV-B register set is identical except the address range is from 0x00−7500 to 0x00−753F. The above registers are mapped to Zone 2. This  
space allows only 16-bit accesses. 32-bit accesses produce undefined results.  
New register compared to 24x/240x  
60  
SPRS174L  
April 2001 − Revised December 2004  
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