Functional Overview
3.7
System Control
This section describes the F281x and C281x oscillator, PLL and clocking mechanisms, the watchdog function
and the low power modes. Figure 3−8 shows the various clock and reset domains in the F281x and C281x
devices that will be discussed.
Reset
XRS
Watchdog
Block
SYSCLKOUT
Peripheral Reset
CLKIN
X1/XCLKIN
X2
C28x
CPU
PLL
OSC
(See Note A)
Power
Modes
Control
XF_XPLLDIS
Clock Enables
System
Control
Registers
Peripheral
Registers
eCAN
I/O
I/O
I/O
LSPCLK
Low-Speed Prescaler
Peripheral
Registers
Low-Speed Peripherals
SCI-A/B, SPI, McBSP
GPIOs
GPIO
MUX
HSPCLK
High-Speed Prescaler
Peripheral
Registers
High-Speed Peripherals
EV-A/B
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC Inputs
NOTE A: CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
Figure 3−8. Clock and Reset Domains
50
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
