Functional Overview
IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals or
External
INTx
MUX
INTx.6
INTx.7
INTx.8
Interrupts
PIEACKx
(Enable/Flag)
(Enable)
(Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
Figure 3−7. Multiplexing of Interrupts Using the PIE Block
†
Table 3−11. PIE Peripheral Interrupts
PIE INTERRUPTS
CPU
INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
PDPINTB
(EV-B)
PDPINTA
(EV-A)
INT1
INT2
INT3
INT4
INT5
INT6
XINT2
XINT1
reserved
T1OFINT
(EV-A)
T1UFINT
(EV-A)
T1CINT
(EV-A)
T1PINT
(EV-A)
CMP3INT
(EV-A)
CMP2INT
(EV-A)
CMP1INT
(EV-A)
reserved
reserved
reserved
reserved
reserved
CAPINT3
(EV-A)
CAPINT2
(EV-A)
CAPINT1
(EV-A)
T2OFINT
(EV-A)
T2UFINT
(EV-A)
T2CINT
(EV-A)
T2PINT
(EV-A)
T3OFINT
(EV-B)
T3UFINT
(EV-B)
T3CINT
(EV-B)
T3PINT
(EV-B)
CMP6INT
(EV-B)
CMP5INT
(EV-B)
CMP4INT
(EV-B)
CAPINT6
(EV-B)
CAPINT5
(EV-B)
CAPINT4
(EV-B)
T4OFINT
(EV-B)
T4UFINT
(EV-B)
T4CINT
(EV-B)
T4PINT
(EV-B)
MXINT
(McBSP)
MRINT
(McBSP)
SPITXINTA
(SPI)
SPIRXINTA
(SPI)
reserved
reserved
reserved
INT7
INT8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ECAN1INT
(CAN)
ECAN0INT
(CAN)
SCITXINTB SCIRXINTB SCITXINTA
SCIRXINTA
(SCI-A)
INT9
reserved
reserved
(SCI-B)
reserved
reserved
reserved
(SCI-B)
reserved
reserved
reserved
(SCI-A)
reserved
reserved
reserved
INT10
INT11
INT12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
†
Out of the 96 possible interrupts, 45 interrupts are currently used. The remaining interrupts are reserved for future devices. These interrupts
can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by
a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 12).
47
April 2001 − Revised December 2004
SPRS174L
TI [ TEXAS INSTRUMENTS ]
