Functional Overview
3.6
Interrupts
Figure 3−6 shows how the various interrupt sources are multiplexed within the F281x and C281x devices.
Peripherals (SPI, SCI, McBSP, CAN, EV, ADC)
(41 Interrupts)
WDINT
Watchdog
WAKEINT
LPMINT
Low-Power Modes
XINT1
Interrupt Control
PIE
XINT1CR(15:0)
XINT1CTR(15:0)
INT1 to INT12
XINT2
Interrupt Control
XINT2CR(15:0)
C28x CPU
XINT2CTR(15:0)
GPIO
MUX
TINT0
TIMER 0
TINT2
TINT1
TIMER 2 (for RTOS)
TIMER 1 (for RTOS)
INT14
INT13
select
enable
NMI
XNMI_XINT13
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
†
Out of a possible 96 interrupts, 45 are currently used by peripherals.
Figure 3−6. Interrupt Sources
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. On the F281x and C281x, 45 of these are used by
peripherals as shown in Table 3−11.
46
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
