Functional Overview
†
Table 3−5. Peripheral Frame 0 Registers
‡
NAME
Device Emulation Registers
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
0x00 0880
0x00 09FF
384
EALLOW protected
0x00 0A00
0x00 0A7F
reserved
128
96
EALLOW protected
CSM Protected
0x00 0A80
0x00 0ADF
§
FLASH Registers
0x00 0AE0
0x00 0AEF
Code Security Module Registers
reserved
16
48
EALLOW protected
0x00 0AF0
0x00 0B1F
0x00 0B20
0x00 0B3F
XINTF Registers
reserved
32
Not EALLOW protected
Not EALLOW protected
0x00 0B40
0x00 0BFF
192
64
0x00 0C00
0x00 0C3F
CPU-TIMER0/1/2 Registers
reserved
0x00 0C40
0x00 0CDF
160
32
0x00 0CE0
0x00 0CFF
PIE Registers
Not EALLOW protected
EALLOW protected
0x00 0D00
0x00 0DFF
PIE Vector Table
Reserved
256
512
0x00 0E00
0x00 0FFF
†
‡
Registers in Frame 0 support 16-bit and 32-bit accesses.
If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS instruction
disables writes. This prevents stray code or pointers from corrupting register contents.
§
The Flash Registers are also protected by the Code Security Module (CSM).
¶
Table 3−6. Peripheral Frame 1 Registers
NAME
eCAN Registers
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
0x00 6000
0x00 60FF
256
(128 x 32)
Some eCAN control registers (and selected bits in other eCAN
control registers) are EALLOW-protected.
0x00 6100
0x00 61FF
256
(128 x 32)
eCAN Mailbox RAM
reserved
Not EALLOW-protected
0x00 6200
0x00 6FFF
3584
¶
The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
41
April 2001 − Revised December 2004
SPRS174L
TI [ TEXAS INSTRUMENTS ]
