Functional Overview
3.2.17 Low-Power Modes
The F281x and C281x devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral will wake the processor from IDLE mode.
STANDBY:
HALT:
Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event.
Turn off oscillator. This mode basically shuts down the device and places it in the lowest
possible power consumption mode. Only a reset or XNMI will wake the device from this
mode.
3.2.18 Peripheral Frames 0, 1, 2 (PFn)
The F281x and C281x segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0:
XINTF:
PIE:
External Interface Configuration Registers (2812 only)
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Control, Programming, Erase, Verify Registers
Flash:
Timers: CPU-Timers 0, 1, 2 Registers
CSM:
eCAN:
SYS:
GPIO:
EV:
Code Security Module KEY Registers
eCAN Mailbox and Control Registers
System Control Registers
PF1:
PF2:
GPIO Mux Configuration and Control Registers
Event Manager (EVA/EVB) Control Registers
McBSP: McBSP Control and TX/RX Registers
SCI:
SPI:
ADC:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Peripheral Interface (SPI) Control and RX/TX Registers
12-Bit ADC Registers
3.2.19 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user
to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured
as inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For
specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise
glitches.
3.2.20 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling.
The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero.
The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter
reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time
OS (RTOS)/BIOS applications. CPU-Timer 1 is also reserved for TI system functions. CPU-Timer 2 is
connected to INT14 of the CPU. CPU-Timer 1 can be connected to INT13 of the CPU. CPU-Timer 0 is for
general use and is connected to the PIE block.
39
April 2001 − Revised December 2004
SPRS174L
TI [ TEXAS INSTRUMENTS ]
