Functional Overview
3.2.21 Control Peripherals
The F281x and C281x support the following peripherals which are used for embedded control and
communication:
EV:
The event manager module includes general-purpose timers, full-compare/PWM units,
capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event
managers are provided which enable two three-phase motors to be driven or four
two-phase motors. The event managers on the F281x and C281x are compatible to the
event managers on the 240x devices (with some minor enhancements).
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.
3.2.22 Serial Port Peripherals
The F281x and C281x support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping
of messages, and is CAN 2.0B-compliant.
McBSP:
This is the multichannel buffered serial port that is used to connect to E1/T1 lines,
phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC
devices. The McBSP receive and transmit registers are supported by a 16-level FIFO. This
significantly reduces the overhead for servicing this peripheral.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multi-device communications are supported by the master/slave operation of
the SPI. On the F281x and C281x, the port supports a 16-level, receive and transmit FIFO
for reducing servicing overhead.
SCI:
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F281x and C281x, the port supports a 16-level, receive and
transmit FIFO for reducing servicing overhead.
3.3
Register Map
The F281x and C281x devices contain three peripheral register spaces. The spaces are categorized as
follows:
•
•
•
Peripheral Frame 0:
Peripheral Frame 1:
Peripheral Frame 2:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 3−5.
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 3−6.
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 3−7.
40
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
