Functional Overview
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING
IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT
TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.
3.2.12 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE
block can support up to 96 peripheral interrupts. On the F281x and C281x, 45 of the possible 96 interrupts
are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU
interrupt lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated
RAM block that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing
the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU
can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each
individual interrupt can be enabled/disabled within the PIE block.
3.2.13 External Interrupts (XINT1, XINT2, XINT13, XNMI)
The F281x and C281x support three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one
non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts
can be selected for negative or positive edge triggering and can also be enabled/disabled (including the
XNMI). The masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid
interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.
3.2.14 Oscillator and PLL
The F281x and C281x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator
circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed
on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is
desired. Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass
mode.
3.2.15 Watchdog
The F281x and C281x support a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can
be disabled if necessary.
3.2.16 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when
a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event
managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of
peripherals to be decoupled from increasing CPU clock speeds.
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SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
