Functional Overview
Table 3−3. Wait States
AREA
WAIT-STATES
0-wait
COMMENTS
M0 and M1 SARAMs
Fixed
Fixed
Peripheral Frame 0
0-wait
0-wait (writes)
2-wait (reads)
Peripheral Frame 1
Fixed
0-wait (writes)
2-wait (reads)
Peripheral Frame 2
L0 & L1 SARAMs
Fixed
Fixed
0-wait
Programmed via the Flash registers. 1-wait-state operation is possible at a
reduced CPU frequency. See Section 3.2.6, Flash (F281x Only), for more
information.
Programmable,
1-wait minimum
OTP (or ROM)
Flash (or ROM)
Programmed via the Flash registers. 0-wait-state operation is possible at
reduced CPU frequency. The CSM password locations are hardwired for
16 wait-states. See Section 3.2.6, Flash (F281x Only), for more information.
Programmable,
0-wait minimum
H0 SARAM
Boot-ROM
0-wait
1-wait
Fixed
Fixed
Programmed via the XINTF registers.
Cycles can be extended by external memory or peripheral.
0-wait operation is not possible.
Programmable,
1-wait minimum
XINTF
3.2
Brief Descriptions
3.2.1 C28x CPU
The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is source
code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant
software investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop
not only their system control software in a high-level language, but also enables math algorithms to be
developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically
are handled by microcontroller devices. This efficiency removes the need for a second processor in many
systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x
to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive
floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical
registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency.
The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables
the C28x to execute at high speeds without resorting to expensive high-speed memories. Special
branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional
operations further improve performance.
C28x and TMS320C2000 are trademarks of Texas Instruments.
34
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
