Electrical Specifications
5.11 Reset, BIO, Interrupt, and MP/MC Timings
Table 5–18 assumes testing over recommended operating conditions and H = 0.5t
c(CO)
(see Figure 5–15,
Figure 5–16, and Figure 5–17).
Table 5–18. Reset, BIO, Interrupt, and MP/MC Timing Requirements
MIN
th(RS)
th(BIO)
th(INT)
th(MPMC)
tw(RSL)
tw(BIO)S
tw(BIO)A
tw(INTH)S
tw(INTH)A
tw(INTL)S
tw(INTL)A
tw(INTL)WKP
tsu(RS)
tsu(BIO)
tsu(INT)
tsu(MPMC)
Hold time, RS after CLKOUT low
Hold time, BIO after CLKOUT low
Hold time, INTn, NMI, after CLKOUT low†
Hold time, MP/MC after CLKOUT low
Pulse duration, RS low‡§
Pulse duration, BIO low, synchronous
Pulse duration, BIO low, asynchronous
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
Setup time, RS before X2/CLKIN low¶
Setup time, BIO before CLKOUT low
Setup time, INTn, NMI, RS before CLKOUT low
Setup time, MP/MC before CLKOUT low
3
4
1
4
4H+3
2H+3
4H
2H+2
4H
2H+2
4H
8
3
7
7
5
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
† The external interrupts (INT0 – INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1–0–0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50
µs
to ensure synchronization
and lock-in of the PLL.
§ Note that RS may cause a change in clock frequency, therefore changing the value of H.
¶ The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT=00 field in the BSCR).
X2/CLKIN
tsu(RS)
tw(RSL)
RS, INTn, NMI
tsu(INT)
th(RS)
CLKOUT
tsu(BIO)
th(BIO)
BIO
tw(BIO)S
Figure 5–15. Reset and BIO Timings
76
SPRS007B
November 2001 – Revised July 2003