Electrical Specifications
CLKOUT
A[22:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
td(MSCL)
td(MSCH)
MSC
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5–12. I/O Read With Externally Generated Wait States
CLKOUT
A[22:0]
D[15:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
td(MSCL)
td(MSCH)
MSC
Leading
Cycle
Wait
States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5–13. I/O Write With Externally Generated Wait States
74
SPRS007B
November 2001 – Revised July 2003