Electrical Specifications
5.14 Multichannel Buffered Serial Port (McBSP) Timing
5.14.1
McBSP Transmit and Receive Timings
Table 5–21 and Table 5–22 assume testing over recommended operating conditions (see Figure 5–21 and
Figure 5–22).
Table 5–21. McBSP T
ransmit and Receive
Timing Requirements
†
tc(BCKRX)
tw(BCKRX)
tsu(BFRH-BCKRL)
th(BCKRL-BFRH)
tsu(BDRV-BCKRL)
th(BCKRL-BDRV)
tsu(BFXH-BCKXL)
th(BCKXL-BFXH)
Cycle time, BCLKR/X
Pulse duration, BCLKR/X high or BCLKR/X low
Setup time external BFSR high before BCLKR low
time,
Hold time external BFSR high after BCLKR low
time,
Setup time BDR valid before BCLKR low
time,
Hold time BDR valid after BCLKR low
time,
Setup time external BFSX high before BCLKX low
time,
Hold time external BFSX high after BCLKX low
time,
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
MIN
4P‡
2P–1‡
8
1
1
2
7
1
2
3
10
1
0
2
ns
ns
ns
ns
ns
ns
MAX
UNIT
ns
ns
tr(BCKRX)
Rise time, BCKR/X
BCLKR/X ext
6
ns
tf(BCKRX)
Fall time, BCKR/X
BCLKR/X ext
6
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ P = 0.5 * processor clock
80
SPRS007B
November 2001 – Revised July 2003
TI [ TEXAS INSTRUMENTS ]
