Electrical Specifications
CLKOUT
A[22:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
td(MCSL)
td(MCSH)
MSC
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5–10. Memory Read With Externally Generated Wait States
CLKOUT
A[22:0]
D[15:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
td(MSCL)
td(MSCH)
MSC
Leading
Cycle
Wait
States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5–11. Memory Write With Externally Generated Wait States
November 2001 – Revised July 2003
SPRS007B
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