Electrical Specifications
5.10 HOLD and HOLDA Timings
Table 5–16 and Table 5–17 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 5–14).
Table 5–16. HOLD and HOLDA Timing Requirements
MIN
tw(HOLD)
tsu(HOLD)
Pulse duration, HOLD low duration
Setup time, HOLD before CLKOUT low
4H+8
7
MAX
UNIT
ns
ns
Table 5–17. HOLD and HOLDA Switching Characteristics
PARAMETER
tdis(CLKL-A)
tdis(CLKL-RW)
tdis(CLKL-S)
ten(CLKL-A)
ten(CLKL-RW)
ten(CLKL-S)
tv(HOLDA)
tw(HOLDA)
CLKOUT
tsu(HOLD)
HOLD
tv(HOLDA)
HOLDA
tv(HOLDA)
tw(HOLD)
tsu(HOLD)
Disable time, Address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, Address, PS, DS, IS valid from CLKOUT low
Enable time, R/W enabled from CLKOUT low
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
Valid time, HOLDA low after CLKOUT low
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
2
–1
–1
2H–3
MIN
MAX
3
3
3
2H+4
2H+3
2H+3
4
4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw(HOLDA)
tdis(CLKL–A)
ten(CLKL–A)
A[22:0]
PS, DS, IS
D[15:0]
tdis(CLKL–RW)
R/W
tdis(CLKL–S)
MSTRB
tdis(CLKL–S)
IOSTRB
ten(CLKL–S)
ten(CLKL–S)
ten(CLKL–RW)
Figure 5–14. HOLD and HOLDA Timings (HM = 1)
November 2001 – Revised July 2003
SPRS007B
75