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TMS320VC5407PGER 参数 Datasheet PDF下载

TMS320VC5407PGER图片预览
型号: TMS320VC5407PGER
PDF下载: 下载PDF文件 查看货源
内容描述: [IC,DSP,16-BIT,QFP,144PIN,PLASTIC]
分类和应用:
文件页数/大小: 107 页 / 1364 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Electrical Specifications
5.8.4 I/O Write
Table 5–13 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t
c(CO)
(see
Figure 5–9).
Table 5–13. I/O Write Switching Characteristics
PARAMETER
Delay time, CLKOUT low to address
valid†
For accesses not immediately following a
HOLD operation
For read accesses immediately following a
HOLD operation
For accesses not immediately following a
HOLD operation
For read accesses immediately following a
HOLD operation
MIN
–1
–1
2H – 3
2H – 5
–1
2H – 5
2H – 5
–1
2H – 2
0
4
4
2H + 6
2H + 6
4
MAX
4
6
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-A)
tsu(A)IOSL
Setu
Setup time, address valid before IOSTRB
low†
Delay time, CLKOUT low to write data valid
Setup time, data valid before IOSTRB high
Hold time, data valid after IOSTRB high
Delay time, CLKOUT low to IOSTRB low
Pulse duration, IOSTRB low
td(CLKL-D)W
tsu(D)IOSH
th(D)IOSH
td(CLKL-IOSL)
tw(SL)IOS
td(CLKL-IOSH)
Delay time, CLKOUT low to IOSTRB high
† Address R/W, PS, DS, and IS timings are included in timings referenced as address.
CLKOUT
td(CLKL-A)
A[22:0]†
td(CLKL-D)W
tsu(A)IOSL
D[15:0]
tsu(D)IOSH
td(CLKL-IOSL)
IOSTRB
td(CLKL-IOSH)
th(D)IOSH
td(CLKL-D)W
R/W†
tw(SL)IOS
IS†
† Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5–9. Parallel I/O Port Write (IOSTRB = 0)
November 2001 – Revised July 2003
SPRS007B
71