TMS320VC5407PGER 参数 Datasheet PDF下载

Functional Overview

3.19.1

IFR and IMR Registers

The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in Figure 3–26.

15

Reserved

14

UART

13

DMAC5

12

DMAC4

11

BXINT1

10

BRINT1

9

HINT

8

INT3†

7

BXINT2

6

BRINT2

5

BXINT0

4

BRINT0

3

TINT0

2

INT2

1

INT1

0

INT0

† Bit 8 reflects the status of either INT3 or TINT1: these two interrupts are ORed together. To distinguish one from the other, one of these two interrupt

sources must be inhibited.

Figure 3–26. IFR and IMR

November 2001 – Revised July 2003

SPRS007B

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