TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
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SPRS439C–JUNE 2007–REVISED FEBRUARY 2008
Active
(A) (B)
(C)
Lead
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
d(XCOHL-XZCSH)
t
d(XCOH-XZCSL)
XZCS0, XZCS6, XZCS7
t
d(XCOH-XA)
XA[0:19]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE0, XWE1(D)
XR/W
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
t
t
dis(XD)XRNW
d(XWEL-XD)
t
t
en(XD)XWEL
h(XD)XWEH
XD[0:31], XD[0:15]
XREADY(E)
DOUT
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles.
D. XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-24. Example Write Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
0
0
≥ 1
≥ 0
≥ 0
N/A(1)
(1) N/A = Not applicable (or “Don’t care”) for this example
6.10.7.7 External Interface Ready-on-Read Timing With One External Wait State
Table 6-41. External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
MIN
MAX
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high to zone chip-select active low
1
3
Delay time, XCLKOUT high/low to zone chip-select inactive
high
- 2
ns
td(XCOH-XA)
td(XCOHL-XRDL)
td(XCOHL-XRDH)
th(XA)XZCSH
th(XA)XRD
Delay time, XCLKOUT high to address valid
2
1
1
ns
ns
ns
ns
ns
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
- 2
(1)
(1)
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Table 6-42. External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
ta(A)
Access time, read data from address valid
(LR + AR) - 16(1)
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-36.
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Electrical Specifications
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