TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
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SPRS439C–JUNE 2007–REVISED FEBRUARY 2008
Trail
(A)(B)
(C)
Active
Lead
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
XA[0:19]
t
d(XCOH-XA)
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
XWE0, XWE1(D)
XR/W
t
su(XD)XRD
t
a(A)
t
h(XD)XRD
t
a(XRD)
XD[0:31], XD[0:15]
XREADY(E)
DIN
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles.
D. XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-23. Example Read Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 1
≥ 0
≥ 0
0
0
N/A(1)
N/A(1)
N/A(1)
N/A(1)
(1) N/A = Not applicable (or “Don’t care”) for this example
6.10.7.6 External Interface Write Timing
Table 6-40. External Interface Write Switching Characteristics
PARAMETER
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE0, XWE1(1) low
Delay time, XCLKOUT high/low to XWE0, XWE1 high
Delay time, XCLKOUT high to XR/W low
1
3
2
2
2
1
1
- 2
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE0, XWE1 low
Delay time, data valid after XWE0, XWE1 active low
Hold time, address valid after zone chip-select inactive high
- 2
0
td(XWEL-XD)
4
(2)
th(XA)XZCSH
th(XD)XWE
Hold time, write data valid after XWE0, XWE1 inactive high
TW-2(3)
tdis(XD)XRNW
Maximum time for DSP to release the data bus after XR/W inactive high
4
(1) XWE1 is used in 32-bit data bus mode only. In 16-bit mode, this signal is XA0.
(2) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
(3) TW = Trail period, write access. See Table 6-36.
142
Electrical Specifications
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