TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
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SPRS439C–JUNE 2007–REVISED FEBRUARY 2008
6.10.7.8 External Interface Ready-on-Write Timing With One External Wait State
Table 6-45. External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE0, XWE1 low(1)
Delay time, XCLKOUT high/low to XWE0, XWE1 high(1)
Delay time, XCLKOUT high to XR/W low
1
3
2
2
2
1
1
– 2
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XR/W high
– 2
0
Enable time, data bus driven from XWE0, XWE1 low(1)
Delay time, data valid after XWE0, XWE1 active low(1)
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high(1)
Maximum time for DSP to release the data bus after XR/W inactive high
td(XWEL-XD)
4
(2)
th(XA)XZCSH
th(XD)XWE
TW-2(3)
tdis(XD)XRNW
4
(1) XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
(3) TW = trail period, write access (see Table 6-36)
Table 6-46. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1)
MIN
15
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
12
ns
te(XRDYsynchH)
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
3
ns
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
15
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-27:
E =(XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is high, then the access will complete. If XREADY (synchronous) is low, it is sampled
again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE +n –1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-47. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1)
MIN
11
8
MAX UNIT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
ns
ns
te(XRDYasynchH)
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
3
ns
tsu(XRDYasynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
11
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-27:
E = (XWRLEAD + XWRACTIVE –2) tc(XTIM). When first sampled, if XREADY (asynchronous) is high, then the access will complete. If
XREADY (asynchronous) is low, it is sampled again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE –3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
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Electrical Specifications
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