TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
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SPRS439C–JUNE 2007–REVISED FEBRUARY 2008
will be with respect to the falling edge of XCLKOUT.
Examples:
XRDH
XWEH
XRD inactive high
XWE1 or XWE0 inactive high
•
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total
number of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will
be with respect to the falling edge of XCLKOUT.
Examples:
XZCSH
Zone chip-select inactive high
XR/W inactive high
XRNWH
6.10.7.5 External Interface Read Timing
Table 6-38. External Interface Read Timing Requirements
MIN
Access time, read data from address valid
MAX
(LR + AR) –16(1)
AR –14(1)
UNIT
ns
ta(A)
ta(XRD)
Access time, read data valid from XRD active low
ns
tsu(XD)XRD
th(XD)XRD
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
14
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-36.
Table 6-39. External Interface Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
1
3
2
1
1
–2
ns
ns
td(XCOHL-XRDL)
td(XCOHL-XRDH
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
ns
–2
(1)
ns
ns
(1)
th(XA)XRD
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
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