TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
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SPRS439C–JUNE 2007–REVISED FEBRUARY 2008
6.10.7.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1
Lead:
LR ≥ × tc(XTIM)
LW ≥ tc(XTIM)
2
Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
3
Lead + Active: LR + AR ≥ 4 × tc(XTIM)
LW + AW ≥ 4 × tc(XTIM)
NOTE
Restrictions do not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 2
0
≥ 1
≥ 2
0
0, 1
or
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 2
≥ 1
0
≥ 2
≥ 1
0
0, 1
Examples of valid and invalid timing when using asynchronous XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid(1)
Invalid(1)
Invalid(1)
Valid
0
1
1
1
1
2
0
0
1
1
2
1
0
0
0
0
0
0
0
1
1
1
1
2
0
0
1
1
2
1
0
0
0
0
0
0
0, 1
0, 1
0
1
Valid
0, 1
0, 1
Valid
(1) No hardware to detect illegal XTIMING configurations
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-37.
Table 6-37. XINTF Clock Configurations
MODE
SYSCLKOUT
XTIMCLK
SYSCLKOUT
150 MHz
XCLKOUT
SYSCLKOUT
150 MHz
1
Example:
2
150 MHz
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
Example:
3
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
Example:
4
150 MHz
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
Example:
150 MHz
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Electrical Specifications
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