TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174S–APRIL 2001–REVISED MARCH 2011
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6.14 Clock Requirements and Characteristics
6.14.1 Input Clock Requirements
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
Table 6-6. Input Clock Frequency
PARAMETER
Resonator
Crystal
MIN
20
20
4
TYP
MAX UNIT
35
35
MHz
150
fx
Input clock frequency
Without PLL
With PLL
XCLKIN
5
100
fl
Limp mode clock frequency
2
MHz
Table 6-7. XCLKIN Timing Requirements – PLL Bypassed or Enabled
NO.
C8
MIN
MAX UNIT
tc(CI)
tf(CI)
Cycle time, XCLKIN
6.67
250
6
ns
ns
ns
%
C9
Fall time, XCLKIN
C10 tr(CI)
Rise time, XCLKIN
6
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
Pulse duration, X1/XCLKIN high as a percentage of tc(CI)
40
40
60
60
%
Table 6-8. XCLKIN Timing Requirements – PLL Disabled
NO.
MIN
MAX UNIT
C8
C9
tc(CI)
tf(CI)
Cycle time, XCLKIN
6.67
250
6
ns
ns
Fall time, XCLKIN
Up to 30 MHz
30 MHz to 150 MHz
Up to 30 MHz
2
C10 tr(CI)
Rise time, XCLKIN
6
ns
%
%
30 MHz to 150 MHz
XCLKIN ≤ 120 MHz
120 < XCLKIN ≤ 150 MHz
2
C11 tw(CIL)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
40
45
40
45
60
55
60
55
C12 tw(CIH)
Pulse duration, X1/XCLKIN high as a percentage of tc(CI) XCLKIN ≤ 120 MHz
120 < XCLKIN ≤ 150 MHz
Table 6-9. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled.
Clock input to the CPU (CLKIN) is directly derived from the clock signal present at
the X1/XCLKIN pin.
PLL Disabled
XCLKIN
Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is
bypassed. However, the /2 module in the PLL block divides the clock input at the
X1/XCLKIN pin by two before feeding it to the CPU.
PLL Bypassed
PLL Enabled
XCLKIN/2
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module in the
PLL block now divides the output of the PLL by two before feeding it to the CPU.
(XCLKIN * n) / 2
102
Electrical Specifications
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