SPRS174S – APRIL 2001 – REVISED MARCH 2011
www.ti.com
Table 6-51. McBSP Switching Characteristics
(1) (2)
NO.
M1
M2
M3
M4
M5
M6
t
c(CKRX)
t
w(CKRXH)
t
w(CKRXL)
t
d(CKRH-FRV)
t
d(CKXH-FXV)
t
dis(CKXH-DXHZ)
Cycle time, CLKR/X
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
Disable time, CLKX high to DX high impedance following last
data bit
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
M7
t
d(CKXH-DXV)
Delay time, CLKX high to DX valid.
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY = 01b or 10b) modes.
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
PARAMETER
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
0
6
P
P+6
ns
0
6
P
P+6
8
14
P+8
P + 14
ns
ns
MIN
2P
D–5
(3)
MAX
D+5
(3)
UNIT
ns
ns
ns
ns
ns
ns
C – 5
(3)
0
3
0
3
C + 5
(3)
4
27
4
27
8
14
9
28
8
14
P+8
P + 14
ns
Enable time, CLKX high to DX driven.
M8
t
en(CKXH-DX)
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY = 01b or 10b) modes.
Delay time, FSX high to DX valid.
M9
t
d(FXH-DXV)
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY = 00b) mode.
Enable time, FSX high to DX driven.
M10
t
en(FXH-DX)
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY = 00b) mode.
(1)
(2)
(3)
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
2P = 1/CLKG in ns.
C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
150
Electrical Specifications
Copyright © 2001–2011, Texas Instruments Incorporated
Product Folder Link(s):
TI [ TEXAS INSTRUMENTS ]
