TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-44. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to PCLK and VPBECLK(1) (see Figure 6-25)
-400
-500
-600
NO.
PARAMETER
UNIT
MIN
MAX
11
12
13
14
29
30
31
32
td(PCLK-VCTLV)
Delay time, PCLK edge to VCTL valid
13
ns
ns
ns
ns
ns
ns
ns
ns
td(PCLK-VCTLIV)
Delay time, PCLK edge to VCTL invalid
2.5
2.5
td(PCLK-VDATAV)
td(PCLK-VDATAIV)
td(VPBECLK-VCTLV)
td(VPBECLK-VCTLIV)
td(VPBECLK-VDATAV)
td(VPBECLK-VDATAIV)
Delay time, PCLK edge to VDATA valid
13
13
13
Delay time, PCLK edge to VDATA invalid
Delay time, VPBECLK rising edge to VCTL valid
Delay time, VPBECLK rising edge to VCTL invalid
Delay time, VPBECLK rising edge to VDATA valid
Delay time, VPBECLK rising edge to VDATA invalid
2.5
TBD
(1) PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising
edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.
VPBECLK
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
11, 29
13, 31
12, 30
14, 32
(A)
VCTL
(B)
VDATA
A. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE
B. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]
Figure 6-25. VPBE Output Timing With Respect to PCLK and VPBECLK
Submit Documentation Feedback
Peripheral Information and Electrical Specifications
233
TI [ TEXAS INSTRUMENTS ]
