TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.10.2.3 VPBE Electrical Data/Timing
Table 6-42. Timing Requirements for VPBE CLK Inputs(1)(2) (see Figure 6-23)
-400
-500
-600
NO.
UNIT
MIN
MAX
TBD
TBD
1
2
3
4
5
6
7
8
tc(PCLK)
Cycle time, PCLK
13.33
0.4P
0.4P
ns
ns
ns
ns
ns
ns
ns
ns
tw(PCLKH)
tw(PCLKL)
Pulse duration, PCLK high
Pulse duration, PCLK low
Transition time, PCLK
tt(PCLK)
tc(VPBECLK)
tw(VPBECLKH)
tw(VPBECLKL)
tt(VPBECLK)
Cycle time, VPBECLK
13.33
0.4V
0.4V
Pulse duration, VPBECLK high
Pulse duration, VPBECLK low
Transition time, VPBECLK
(1) P = PCLK period in ns.
(2) V = VPBECLK period in ns.
3
7
1
5
2
PCLK
4
4
6
VPBECLK
8
8
Figure 6-23. VPBE PCLK and VPBECLK Timing
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Peripheral Information and Electrical Specifications
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