TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-6. DM6437 EDMA Channel Synchronization Events (continued)
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
37
38
GPINT5
GPINT6
GPIO 5 Interrupt
GPIO 6 Interrupt
39
GPINT7
GPIO 7 Interrupt
40
GPBNKINT0
GPBNKINT1
GPBNKINT2
GPBNKINT3
GPBNKINT4
GPBNKINT5
GPBNKINT6
–
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
GPIO Bank 6 Interrupt
Reserved
41
42
43
44
45
46
47
48
TEVTL0
TEVTH0
TEVTL1
TEVTH1
PWM0
Timer 0 Event Low Interrupt
Timer 0 Event High Interrupt
Timer 1 Event Low Interrupt
Timer 1 Evemt High Interrupt
PWM 0 Event
49
50
51
52
53
PWM1
PWM 1 Event
54
PWM2
PWM 2 Event
55-63
–
Reserved
176
Peripheral Information and Electrical Specifications
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