TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-7. DM6437 EDMA Registers (continued)
HEX ADDRESS
0x01C0 1084
ACRONYM
QEER
REGISTER NAME
QDMA Event Enable Register
0x01C0 1088
QEECR
QEESR
QSER
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x01C0 108C
0x01C0 1090
0x01C0 1094
QSECR
0x01C0 1098 - 0x01C0 1FFF
Shadow Region 0 Channel Registers
0x01C0 2000
0x01C0 2004
0x01C0 2008
0x01C0 200C
0x01C0 2010
0x01C0 2014
0x01C0 2018
0x01C0 201C
0x01C0 2020
0x01C0 2024
0x01C0 2028
0x01C0 202C
0x01C0 2030
0x01C0 2034
0x01C0 2038
0x01C0 203C
0x01C0 2040
0x01C0 2044
0x01C0 2048 - 0x01C0 204C
0x01C0 2050
0x01C0 2054
0x01C0 2058
0x01C0 205C
0x01C0 2060
0x01C0 2064
0x01C0 2068
0x01C0 206C
0x01C0 2070
0x01C0 2074
0x01C0 2078
0x01C0 207C
0x01C0 2080
0x01C0 2084
0x01C0 2088
0x01C0 208C
0x01C0 2090
0x01C0 2094
0x01C0 2098 - 0x01C0 21FC
ER
ERH
Event Register
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register High
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
-
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
IERH
IECR
IECRH
IESR
IESRH
IPR
IPRH
ICR
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
QER
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
Shadow Region 1 Channel Registers
0x01C0 2200
ER
Event Register
180
Peripheral Information and Electrical Specifications
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