TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
MXI/CLKIN Clock Rate
32
DSP/6 Clock Rate
DSP/6 Clock Rate
32
32
UART0
UART1
HECC
I2C
Bridge 8
DDR2 Memory
Controller
(Memory/Register)
32
64
64
64
VLYNQ
EMAC
HPI
32
32
32
32
32
32
32
32
64
Bridge 2
SCR 5
HPI
32
64x+
L2/L1
VPSS Reg
EMAC Reg
32
32
32
32
32
32
32
32
32
PWM0
PWM1
PWM2
Timer0
Timer1
Timer2
PCI (Slave
Back-End I/F)
32
64
64
Bridge 1
32
32
SCR 2
32
PCI
(Master Back-End I/F)
Bridge 7
EMAC Control
Module Reg
32
32
VPSS
EMAC Control
Module RAM
SCR 6
64
64
Read
64
64
Bridge 5
Bridge 4
MDIO
EDMA3TC0
EDMA3TC1
EDMA3TC2
SCR 1
Write
Read
Write
Read
Write
32
64
32
32
GPIO
64
64
64
32
32
System Reg
PSC
32
32
Bridge 6
PLLC1
PLLC2
64
Bridge 3
SCR 3
32
PCI Reg
L2 Cache
32
32
EMIFA
VLYNQ
SCR 4
32
SCR 7
64
32
EDMA3CC
64x+
32
32
EDMA3TC0
EDMA3TC1
EDMA3TC2
32
McBSP0
McBSP1
32
SCR 8
32
McASP0
DSP/3 Clock Rate
DSP/3 Clock Rate
DSP/6 Clock Rate
MXI/CLKIN Clock Rate
Figure 4-1. System Interconnect Block Diagram
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System Interconnect
161
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