TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
b. Peripherals configuration: see the respective peripheral user’s guide.
Special considerations: DDR2 memory controller—the Peripheral Bus Burst Priority Register
(PBBPR) should be programmed to ensure good DDR2 throughput and to prevent command
starvation (prevention of certain commands from being processed by the DDR2 memory controller).
For more details, see the TMS320DM643x DMP DDR2 Memory Controller User’s Guide (literature
number SPRU986). A hex value of 0x20 is recommended for the PBBPR PR_OLD_COUNT field to
provide a good DSP performance and still allow good utilization by other modules.
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Device Configurations
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