TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
3.7.3.6 UART0 Data Block Muxing
This block of 2 pins consists of UART0 Data and GPIO muxed pins. The PINMUX1.UR0DBK register field
select the pin functions in the UART0 Data Block.
Table 3-27 summarizes the 2 pins in the UART0 Data Block, the multiplexed function on each pin, and the
PINMUX configurations to select the corresponding function.
Table 3-27. UART0 Data Block Muxed Pins Selection
MULTIPLEXED FUNCTIONS
SIGNAL
UART0
GPIO
NAME
FUNCTION
URXD0
SELECT
FUNCTION
GP[85]
SELECT
URXD0/GP[85]
UTXD0/GP[86]
UR0DBK = 1
UR0DBK = 0
UTXD0
GP[86]
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the UART0 pins span
across two Pin Mux Blocks: UART0 Data Block, and UART0 Flow Control Block. For proper UART0
operation, the two pins in the UART0 Data Block must be configured for UART0 data functions. The two
pins in the UART0 Flow Control Block are optional.
Table 3-28 provides a different view of the UART0 Data Block pin muxing, showing the UART0 Data Block
function based on PINMUX1.UR0DBK setting. The selection options are also shown pictorially in
Figure 3-11.
Table 3-28. UART0 Data Block Function Selection
PINMUX1.UR0DBK
BLOCK FUNCTION
GPIO (2) (default)
UART0 Data
RESULTING PIN FUNCTIONS
GPIO: GP[86:85]
0
1
UART0: URXD0, UTXD0
In addition, the VDD3P3V_PWDN.UR0DAT field determines the power state of the UART0 Data Block
pins. The UART0 Data Block pins default to powered down and not operational. To use these pins, user
must first program VDD3P3V_PWDN.UR0DAT = 0 to power up the pins. For more details on the
VDD3P3V_PWDN.UR0DAT field, see Section 3.2, Power Considerations.
The UART0 Data Block features internal pullup resistors, which matches the UART inactive polarity.
3.7.3.7 UART0 Flow Control Block
This block of 2 pins consists of UART0 Flow Control, PWM0, and GPIO muxed pins. The
PINMUX1.UR0FCBK register field selects the pin functions in the UART0 Flow Control Block.
Table 3-29 summarizes the 2 pins in the UART0 Flow Control Block, the multiplexed function on each pin,
and the PINMUX configurations to select the corresponding function.
Table 3-29. UART0 Flow Control Block Muxed Pins Selection
MULTIPLEXED FUNCTIONS
SIGNAL
UART0
PWM0
GPIO
NAME
FUNCTION
SELECT
FUNCTION
SELECT
FUNCTION
SELECT
UCTS0/
GP[87]
UCTS0
–
–
GP[87]
UR0FCBK = 00/10
UR0FCBK = 01
URTS0/
PWM0/
GP[88]
URTS0
PWM0
UR0FCBK = 10
GP[88]
UR0FCBK = 00
Submit Documentation Feedback
Device Configurations
123
TI [ TEXAS INSTRUMENTS ]
