TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, PCI pins span across the
following Pin Mux Blocks: Host Block, EMIFA/VPSS Block Sub-Block 0 and Sub-Block 3, PCI Data Block,
and GPIO Block. For proper PCI operation, PCI must be selected in all of these Pin Mux Blocks.
Table 3-23 provides a different view of the Host Block pin muxing, showing the Host Block function based
on PINMUX1 settings. The selection options are also shown pictorially in Figure 3-11.
If EMAC operation is desired, EMAC must be placed in reset before programming PINMUX1.HOSTBK to
select EMAC pins.
Table 3-23. Host Block Function Selection
PINMUX1 SETTING
BLOCK FUNCTION
RESULTING PIN FUNCTIONS
PCIEN(1)
HOSTBK
PCI: PCICLK, PCBE2, PCBE1, PCBE0, PFRAME, PIDRDY, PTRDY,
PDEVSEL, PSTOP, PPER, PSERR, PPAR, AD[18:05], AD[03]
PCI
1
000
(Default if PCIEN = 1)
Internal pullup/pulldown on all these pins are disabled.
Reserved
1
0
001 to 111
000
Reserved
GPIO (27)
(Default if PCIEN = 0)
GPIO: GP[83:57]
HPI: HHWIL, HCNTL[1:0], HR/W, HDS2, HDS1, HRDY, HCS, HINT, HAS,
0
0
001
010
HPI + GPIO (1)
HD[15:0]
GPIO: GP[57]
VLYNQ: VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],
VLYNQ_TXD[3:0]
VLYNQ + GPIO (17)
GPIO: GP[83:67]
VLYNQ: VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],
VLYNQ_TXD[3:0]
EMAC (MII): TXCLK, CRS, COL, TXD[3:0], RXDV, TXEN, RXER, RXCLK,
0
011
VLYNQ + EMAC (MII) + MDIO
RXD[3:0]
MDIO: MDC, MDIO
If EMAC operation is desired, EMAC must be placed in reset before
programming PINMUX1.HOSTBK to select EMAC pins.
EMAC (MII): TXCLK, CRS, COL, TXD[3:0], RXDV, TXEN, RXER, RXCLK,
RXD[3:0]
MDIO: MDC, MDIO
GPIO: GP[66:57]
0
0
100
EMAC (MII) + MDIO + GPIO (10)
If EMAC operation is desired, EMAC must be placed in reset before
programming PINMUX1.HOSTBK to select EMAC pins.
101 to 111
Reserved
Reserved
(1) If PCIEN = 1, the internal pullup/pulldown on all Host Block pins are disabled. If PCIEN = 0, the internal pullup/pulldown on all Host
Block pins are enabled.
The PINMUX1.PCIEN field is read-only, and its setting is determined by the PCIEN configuration pin.
Based on the PCIEN configuration pin setting, the 27 pins in the Host Block defaults to either PCI or GPIO
function.
In addition, the VDD3P3V_PWDN.HOST field determines the power state of the Host Block pins. The
Host Block pins default to powered up. For more details on the VDD3P3V_PWDN.HOST field, see
Section 3.2, Power Considerations.
120
Device Configurations
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