TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 3-21. Multiplexed Pins on DM6437 (continued)
SIGNAL
PINMUX DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
EM_A[5]/AD19/GP[96]
PINMUX GROUP
CONTROLLED BY PINMUX BIT FIELDS
B8
A7
C8
D7
A8
B7
C7
A6
D6
B6
A5
C6
B5
C5
D5
B4
D4
A4
C4
D3
B3
A3
C3
B2
D2
C1
C2
D1
E1
E2
E3
E4
F3
H1
H4
J2
A10
A8
B9
C9
A9
B8
C8
A7
C7
B7
A6
C6
B6
A5
C5
B4
B5
A4
D3
C4
B2
A3
C2
B3
C3
D1
D2
C1
E1
E2
F1
F2
F3
J1
EMIFA/VPSS Sub-Block 3
Host Block
PCIEN, AEM
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN, HOSTBK
PCIEN
VLYNQ_CLOCK/PCICLK/GP[57]
HD0/VLYNQ_SCRUN/AD18/GP[58]
HD1/VLYNQ_RXD0/AD16/GP[59]
HD2/VLYNQ_RXD1/AD17/GP[60]
HD3/VLYNQ_RXD2/PCBE2/GP[61]
HD4/VLYNQ_RXD3/PFRAME/GP[62]
HD5/VLYNQ_TXD0/PIRDY/GP[63]
HD6/VLYNQ_TXD1/PTRDY/GP[64]
HD7/VLYNQ_TXD2/PDEVSEL/GP[65]
HD8/VLYNQ_TXD3/PPERR/GP[66]
HD9/MCOL/PSTOP/GP[67]
HD10/MCRS/PSERR/GP[68]
HD11/MTXD3/PCBE1/GP[69]
HD12/MTXD2/PPAR/GP[70]
HD13/MTXD1/AD14/GP[71]
HD14/MTXD0/AD15/GP[72]
HD15/MTXCLK/AD12/GP[73]
HHWIL/MRXDV/AD13/GP[74]
HCNTL1/MTXEN/AD11/GP[75]
HCNTL0/MRXER/AD10/GP[76]
HR/W/MRXCLK/AD8/GP[77]
HDS2/MRXD0/AD9/GP[78]
HDS1/MRXD1/AD7/GP[79]
HRDY/MRXD2/PCBE0/GP[80]
HCS/MDCLK/AD5/GP[81]
HINT/MRXD3/AD6/GP[82]
HAS/MDIO/AD3/GP[83]
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
Host Block
AD0/GP[0]
GPIO Block
AD1/GP[1]
GPIO Block
PCIEN
AD2/GP[2]
GPIO Block
PCIEN
AD4/GP[3]
GPIO Block
PCIEN
GP[4]/PWM1
PWM1Block
PWM1BK
ACLKR0/CLKX0/GP[99]
Serial Port Sub-Block 0
Serial Port Sub-Block 0
Serial Port Sub-Block 0
Serial Port Sub-Block 0
Serial Port Sub-Block 0
Serial Port Sub-Block 0
Serial Port Sub-Block 1
Serial Port Sub-Block 1
Serial Port Sub-Block 1
Serial Port Sub-Block 1
Serial Port Sub-Block 1
Serial Port Sub-Block 1
SPBK0
AFSR0/DR0/GP[100]
K3
K1
J3
SPBK0
AHCLKR0/CLKR0/GP[101]
AXR0[3]/FSR0/GP[102]
SPBK0
G4
H3
J3
SPBK0
AXR0[2]/FSX0/GP[103]
J2
SPBK0
AXR0[1]/DX0/GP[104]
K2
H2
G1
G2
H1
G3
H3
SPBK0
AXR0[0]/FSR1/GP[105]
H2
F1
G2
G1
F2
G3
SPBK1
ACLKX0/CLKX1/GP[106]
AFSX0/DX1/GP[107]
SPBK1
SPBK1
AHCLKX0/CLKR1/GP[108]
AMUTEIN0/FSX1/GP[109]
AMUTE0/DR1/GP[110]
SPBK1
SPBK1
SPBK1
116
Device Configurations
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