TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 3-2
Device State Control Registers (Part 3 of 4)
Address Start
0x02620260
0x0262027C
0x02620280
0x02620284
0x02620288
0x0262028C
0x02620290
0x02620294
0x02620298
0x0262029C
0x026202A0
0x026202BC
0x026202C0
0x02620300
0x02620304
0x02620308
0x0262030C
0x02620310
0x02620314
0x02620318
0x0262031C
0x02620320
0x02620324
0x02620328
0x0262032C
0x02620330
0x02620334
0x02620338
0x0262033C
Address End
0x0262027B
0x0262027F
0x02620283
0x02620287
0x0262028B
0x0262028F
0x02620293
0x02620297
0x0262029B
0x0262029F
0x026202BB
0x026202BF
0x026202FF
0x02620303
0x02620307
0x0262030B
0x0262030F
0x02620313
0x02620317
0x0262031B
0x0262031F
0x02620323
0x02620327
0x0262032B
0x0262032F
0x02620333
0x02620337
0x0262033B
0x0262033F
Size
28B
4B
4B
4B
4B
4B
4B
4B
4B
4B
28B
4B
64B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
Field
Description
Reserved
IPCGRH
See section 3.3.15
See section 3.3.14
IPCAR0
IPCAR1
IPCAR2
IPCAR3
IPCAR4
IPCAR5
IPCAR6
IPCAR7
Reserved
IPCARH
See section 3.3.16
Reserved
TINPSEL
See section 3.3.17
See section 3.3.18
TOUTPSEL
RSTMUX0
RSTMUX1
RSTMUX2
RSTMUX3
RSTMUX4
RSTMUX5
RSTMUX6
RSTMUX7
MAINPLLCTL0
MAINPLLCTL1
DDR3PLLCTL0
DDR3PLLCTL1
PASSPLLCTL0
PASSPLLCTL1
See section 3.3.19
See section 7.5 ‘‘Main PLL and PLL Controller’’ on page 139
See section 7.6 ‘‘DD3 PLL’’ on page 151
See section 7.7 ‘‘PASS PLL’’ on page 154
Copyright 2013 Texas Instruments Incorporated
Device Configuration 77
TI [ TEXAS INSTRUMENTS ]
