TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 7-42
CIC3 Event Inputs (Secondary Events for EDMA3CC0 and HyperLink) (Part 3 of 3)
Input Event # on CIC
System Interrupt
TRACER_CORE_5_INTD
TRACER_CORE_6_INTD
TRACER_CORE_7_INTD
DDR3_ERR
Description
58
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
DDR3 EMIF Error interrupt
59
60
61
62-79
Reserved
End of Table 7-42
7.9.2 CIC Registers
This section includes the offsets for CIC registers. The base addresses for interrupt control registers are CIC0 -
0x0260 0000, CIC1 - 0x0260 4000, CIC2 - 0x0260 8000, and CIC3 - 0x0260 C000.
7.9.2.1 CIC0/CIC1 Register Map
Table 7-43
CIC0/CIC1 Register
Address Offset
0x0
Register Mnemonic
REVISION_REG
Register Name
Revision Register
0x10
GLOBAL_ENABLE_HINT_REG
STATUS_SET_INDEX_REG
STATUS_CLR_INDEX_REG
ENABLE_SET_INDEX_REG
ENABLE_CLR_INDEX_REG
HINT_ENABLE_SET_INDEX_REG
HINT_ENABLE_CLR_INDEX_REG
RAW_STATUS_REG0
RAW_STATUS_REG1
RAW_STATUS_REG2
RAW_STATUS_REG3
RAW_STATUS_REG4
ENA_STATUS_REG0
ENA_STATUS_REG1
ENA_STATUS_REG2
ENA_STATUS_REG3
ENA_STATUS_REG4
ENABLE_REG0
Global Host Int Enable Register
Status Set Index Register
Status Clear Index Register
Enable Set Index Register
Enable Clear Index Register
Host Int Enable Set Index Register
Host Int Enable Clear Index Register
Raw Status Register 0
0x20
0x24
0x28
0x2C
0x34
0x38
0x200
0x204
0x208
0x20C
0x210
0x280
0x284
0x288
0x28c
0x290
0x300
0x304
0x308
0x30c
0x310
0x380
0x384
0x388
0x38c
0x390
0x400
0x404
Raw Status Register 1
Raw Status Register 2
Raw Status Register 3
Raw Status Register 4
Enabled Status Register 0
Enabled Status Register 1
Enabled Status Register 2
Enabled Status Register 3
Enabled Status Register 4
Enable Register 0
ENABLE_REG1
Enable Register 1
ENABLE_REG2
Enable Register 2
ENABLE_REG3
Enable Register 3
ENABLE_REG4
Enable Register 4
ENABLE_CLR_REG0
ENABLE_CLR_REG1
ENABLE_CLR_REG2
ENABLE_CLR_REG3
ENABLE_CLR_REG4
CH_MAP_REG0
Enable Clear Register 0
Enable Clear Register 1
Enable Clear Register 2
Enable Clear Register 3
Enable Clear Register 4
Interrupt Channel Map Register for 0 to 0+3
Interrupt Channel Map Register for 4 to 4+3
CH_MAP_REG1
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 181
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